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for the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468. general description the max1458 highly integrated analog-sensor signal processor is optimized for piezoresistive sensor calibra- tion and compensation without any external compo- nents. it includes a programmable current source for sensor excitation, a 3-bit programmable-gain amplifier (pga), a 128-bit internal eeprom, and four 12-bit dacs. achieving a total error factor within 1% of the sensor? repeatability errors, the max1458 compen- sates offset, offset temperature coefficient, full-span output (fso), fso temperature coefficient (fsotc), and fso nonlinearity of silicon piezoresistive sensors. the max1458 calibrates and compensates first-order temperature errors by adjusting the offset and span of the input signal via digital-to-analog converters (dacs), thereby eliminating quantization noise. built-in testabili- ty features on the max1458 result in the integration of three traditional sensor-manufacturing operations into one automated process: pretest: data acquisition of sensor performance under the control of a host test computer. calibration and compensation: computation and storage (in an internal eeprom) of calibration and compensation coefficients computed by the test computer and downloaded to the max1458. final test operation: verification of transducer cali- bration and compensation without removal from the pretest socket. although optimized for use with piezoresistive sensors, the max1458 may also be used with other resistive sensors (i.e., accelerometers and strain gauges) with some additional external components. ______________________customization maxim can customize the max1458 for unique require- ments. with a dedicated cell library consisting of more than 90 sensor-specific functional blocks, maxim can quickly provide customized max1458 solutions. please contact maxim for further information. ________________________applications piezoresistive pressure and acceleration transducers and transmitters map (manifold absolute pressure) sensors automotive systems hydraulic systems industrial pressure sensors features ? medium accuracy (?%), single-chip sensor signal conditioning ? sensor errors trimmed using correction coefficients stored in internal eeprom eliminates the need for laser trimming and potentiometers ? compensates offset, offset-tc, fso, fsotc, fso linearity ? programmable current source (0.1ma to 2.0ma) for sensor excitation ? fast signal-path settling time (<1ms) ? accepts sensor outputs from 10mv/v to 40mv/v ? fully analog signal path max1458 1%-accurate, digitally trimmed sensor signal conditioner ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sclk limit v dd inp bdrive inm i.c. out isrc top view max1458 ssop cs i.c. dio temp fsotc we v ss 19-1373; rev 0; 5/98 part max1458cae max1458c/d max1458aae -40? to +125? 0? to +70? 0? to +70? temp. range pin-package 16 ssop dice* 16 ssop * dice are tested at t a = +25?, dc parameters only. functional diagram appears at end of data sheet. pin configuration ordering information
max1458 1%-accurate, digitally t rimmed sensor signal conditioner 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +5v, v ss = 0, t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v dd to v ss ...................................... -0.3v to +6v all other pins ................................... (v ss - 0.3v) to (v dd + 0.3v) short-circuit duration, fsotc, out, bdrive ........... continuous continuous power dissipation (t a = +70 c) ssop (derate 8.00mw/ c above +70 c) ..................... 640mw operating temperature ranges max1458cae ...................................................... 0 c to +70 c max1458aae ................................................. -40 c to +125 c storage temperature range ............................. -65 c to +160 c lead temperature (soldering, 10sec) ............................. +300 c (note 1) dc to 10hz (gain = 41, source impedance = 5k ) v limit = 4.6v, v out = (v ss + 0.25v) to (v limit - 0.3v) at minimum gain (note 4) from v ss to v dd t a = t min to t max selectable in eight steps 63% of final value (notes 2, 3) (note 5) conditions v rms 500 output noise ma -0.45 0.45 (sink) (source) output current range v ss + 0.15 v dd - 0.25 ppm/ c 50 differential signal-gain tempco v/v 36 41 45 minimum differential signal gain v/v 41 to 230 differential signal-gain range mv/v 10 to 40 input-referred adjustable fso range ma 3 6 i dd supply current v 4.5 5.0 5.5 v dd supply voltage mv 150 input-referred adjustable offset range db 90 cmrr common-mode rejection ratio ms 1 output step response m 1 r in input impedance v/ c 0.5 input-referred offset tempco %v dd 0.01 amplifier gain nonlinearity units min typ max symbol parameter 10k load to v ss or v dd v limit = 4.6v v output voltage swing v ss + 0.25 v limit 0.3 v ss + 0.1 v limit 0.2 no load general characteristics analog input (pga) analog output (pga) v limit = 5.0v, no load
electrical characteristics (continued) (v dd = +5v, v ss = 0, t a = +25 c, unless otherwise noted.) note 1: excludes the sensor or load current. note 2: all electronics temperature errors are compensated together with sensor errors. note 3: the sensor and the max1458 must always be at the same temperature during calibration and use. note 4: this is the maximum allowable sensor offset. note 5: this is the sensor? sensitivity normalized to its drive voltage, assuming a desired full-span output of 4v and a bridge voltage of 2.5v. note 6: bit weight is ratiometric to v dd . max1458 1%-accurate, digitally t rimmed sensor signal conditioner _______________________________________________________________________________________ 3 typically 4600ppm/ c tempco v fsotc = 2.5v no load input referred, v dd = 5v (note 6) conditions k 100 r temp temperature-dependent resistor k 75 r ftc fso trim resistor k 75 r isrc current-source reference resistor v v ss + 1.3 v dd - 1.3 v bdrive bridge voltage swing ma 0.1 0.5 2.0 i bdrive bridge current range a -20 20 current drive v v ss + 0.3 v dd - 1.3 output voltage swing bits 3 dac resolution mv/bit 9 dac bit weight units min typ max symbol parameter lsb 1.5 dnl differential nonlinearity bits 12 dac resolution v v ss + 1.3 v dd - 1.3 v isrc reference input voltage range (isrc) dac reference = v bdrive = 2.5v dac reference = v dd = 5.0v mv/bit 1.4 ? v out ? code offset tc dac bit weight mv/bit 2.8 ? v out ? code offset dac bit weight dac reference = v bdrive = 2.5v dac reference = v dd = 5.0v mv/bit 0.6 ? v fsotc ? code fso tc dac bit weight mv/bit 1.22 ? v isrc ? code fso dac bit weight current source digital-to-analog converters iro dac fsotc buffer internal resistors
_______________ detailed description the max1458 provides an analog amplification path for the sensor signal. calibration and temperature com - pensation are achieved by varying the offset and gain of a programmable-gain amplifier (pga) and by varying the sensor bridge current. the pga uses a switched- capacitor cmos technology, with an input-referred coarse offset trimming range of approximately 63mv (9mv steps). an additional output-referred fine offset trim is provided by the offset dac (approximately 2.8mv steps). the pga provides eight gain values from +41v/v to +230v/v. the bridge current source is pro - grammable from 0.1ma to 2ma. the max1458 uses four 12-bit dacs and one 3-bit dac, with calibration coefficients stored by the user in an internal 128-bit eeprom. this memory contains the following information as 12-bit-wide words: configuration register offset calibration coefficient offset temperature error compensation coefficient fso (full-span output) calibration coefficient fso temperature error compensation coefficient 24 user-defined bits for customer programming of manufacturing data (e.g., serial number and date) figure 1 shows a typical pressure-sensor output and defines the offset, full-scale, and full-span output values as a function of voltage. max1458 1%-accurate, digitally t rimmed sensor signal conditioner 4 _______________________________________________________________________________________ name function 1 sclk data clock input. used only during programming/testing. internally pulled to v ss with a 1m (typical) resis - tor. data is clocked in on the rising edge of the clock. the maximum sclk frequency is 10khz. 2 cs chip-select input. the max1458 is selected when this pin is high. when low, out and dio become high impedance. internally pulled to v dd with a 1m (typical) resistor. leave unconnected for normal operation. pin 3, 11 i.c. internally connected. leave unconnected. 4 temp temperature sensor output. an internal temperature sensor (a 100k , 4600ppm/ c tc resistor) which can provide a temperature-dependent voltage. 8 v ss negative power-supply input 7 we dual-function input pin. used to enable eeprom erase/write operations. also used to set the dac refresh- rate mode. internally pulled to v dd with a 1m (typical) resistor. refer to the chip-select (cs) and write- enable (we) section. 6 dio data input/output. used only during programming/testing. internally pulled to v ss with a 1m (typical) resistor. high impedance when cs is low. 5 fsotc buffered fsotc dac output. an internal 75k resistor (r ftc ) connects fsotc to isrc (see functional diagram ). optionally, external resistors can be used in place of or in parallel with r ftc and r isrc . 14 inp positive sensor input. input impedance >1m . rail-to-rail input range. 13 bdrive sensor excitation current output. this current source drives the bridge. 12 inm negative sensor input. input impedance >1m . rail-to-rail input range. 10 out pga output voltage 9 isrc current-source reference. an internal 75k resistor (r isrc ) connects isrc to v ss (see functional diagram ). optionally, external resistors can be used in place of or in parallel with r ftc and r isrc . pin description 16 limit voltage limit input. this pin sets the maximum voltage at out. if left unconnected, the output voltage will be limited to 4.6v (v dd = 5v). connect to v dd for maximum output swing. the acceptable range is 4.5v v limit v dd . 15 v dd positive power-supply input. connect a 0.1 f capacitor from v dd to v ss.
fsotc compensation silicon piezoresistive transducers (prts) exhibit a large positive input resistance tempco (tcr) so that, while under constant current excitation, the bridge voltage (v bdrive ) increases with temperature. this depen - dence of v bdrive on the sensor temperature can be used to compensate the sensor temperature errors. prts also have a large negative full-span output sensi - tivity tempco (tcs) so that, with constant voltage exci - tation, full-span output (fso) will decrease with temperature, causing a full-span output temperature coefficient (fsotc) error. however, if the bridge volt - age can be made to increase with temperature at the same rate that tcs decreases with temperature, the fso will remain constant. fsotc compensation is accomplished by resistor r ftc and the fsotc dac, which modulate the excita - tion reference current at isrc as a function of tempera - ture (figure 3). fso dac sets v isrc and remains constant with temperature while the voltage at fsotc varies with temperature. fsotc is the buffered output of the fsotc dac. the reference dac voltage is v bdrive , which is temperature dependent. the fsotc dac alters the tempco of the current source. when the tempco of the bridge voltage is equal in magnitude and opposite in polarity to the tcs, the fsotc errors are compensated and fso will be constant with tempera - ture. offset tc compensation compensating offset tc errors involves first measuring the uncompensated offset tc error, then determining the percentage of the temperature-dependent voltage v bdrive that must be added to the output summing junction to correct the error. use the offset tc dac to adjust the amount of bdrive voltage that is added to the output summing junction (figure 2). analog signal path the fully differential analog signal path consists of four stages: front-end summing junction for coarse offset correction 3-bit pga with eight selectable gains ranging from 41 through 230 three-input-channel summing junction differential to single-ended output buffer (figure 2) coarse offset correction the sensor output is first fed into a differential summing junction (inm (negative input) and inp (positive input)) with a cmrr > 90db, an input impedance of approxi - mately 1m , and a common-mode input voltage range from v ss to v dd . at this summing junction, a coarse off - set-correction voltage is added, and the resultant volt - age is fed into the pga. the 3-bit (plus sign) input-referred offset dac (iro dac) generates the coarse offset-correction voltage. the dac voltage ref - erence is 1.25% of v dd ; thus, a v dd of 5v results in a front-end offset-correction voltage ranging from -63mv to +63mv, in 9mv steps (table 1). to add an offset to the input signal, set the iro sign bit high; to subtract an offset from the input signal, set the iro sign bit low. the iro dac bits (c2, c1, c0, and iro sign bit) are programmed in the configuration register (see internal eeprom section). max1458 1%-accurate, digitally t rimmed sensor signal conditioner _______________________________________________________________________________________ 5 voltage (v) pressure p min p max full-scale (fs) 4.5 0.5 full-span output (fso) offset figure 1. typical pressure-sensor output sotc bdrive 1.25% v dd soff a2 inp inm a1 a0 pga s s a = 1 out limit a = 2.3 a = 2.3 offtc dac iro dac v dd offset dac figure 2. signal-path block diagram
max1458 table 1. input-referred offset dac correction values programmable-gain amplifier the programmable-gain amplifier (pga), which is used to set the coarse fso, uses a switched-capacitor cmos technology and contains eight selectable gain levels from 41 to 230, in increments of 27 (table 2). the output of the pga is fed to the output summing junc - tion. the three pga gain bits a2, a1, and a0 are stored in the configuration register. output summing junction the third stage in the analog signal path consists of a summing junction for the pga output, offset correction, and the offset tc correction. both the offset and the off - set tc correction voltages are gained by a factor of 2.3 before being fed into the summing junction, increasing the offset and offset tc correction range. the offset sign bit and offset tc sign bit are stored in the configu - ration register. the offset sign bit determines if the off - set correction voltage is added to (sign bit is high) or subtracted from (sign bit is low) the pga output. negative offset tc errors require a logic high for the offset tc sign bit. alternately, positive offset tc errors dictate a logic low for the offset tc sign bit. the output of the summing junction is fed to the output buffer. output buffer out can drive 0.1 f of capacitance. if cs is brought low, out becomes high impedance (resulting in typical output impedance of 1m ). the output is current limit - ed and can be shorted to either v dd or v ss indefinitely. the maximum output voltage can be limited using the limit pin. output limiting can be performed for sensor diagnostic purposes. connect limit to v dd to disable the voltage-limiting feature. bridge drive fine fso correction is accomplished by varying the sensor excitation current with the 12-bit fso dac (figure 3). sensor bridge excitation is performed by a programmable current source capable of delivering up to 2ma. the reference current at isrc is established by resistor r isrc and by the voltage at node isrc (con - trolled by the fso dac). the reference current flowing through this pin is multiplied by a current mirror (aa @ 14) and then made available at bdrive for sensor exci - tation. modulation of this current with respect to tem - perature can be used to correct fsotc errors, while modulation with respect to the output voltage (v out ) can be used to correct fso linearity errors. digital-to-analog converters the four 12-bit, sigma-delta dacs typically settle in less than 100ms. the four dacs have a corresponding memory register in eeprom for storage of correction coefficients. use the fso dac for fine fso adjustments. the fso dac takes its reference from v dd and controls v isrc which, in conjunction with r isrc , sets the baseline sen - sor excitation current. the offset dac also takes its ref - erence from v dd and provides a 1.22mv resolution with 1%-accurate, digitally t rimmed sensor signal conditioner 6 _______________________________________________________________________________________ +7 1 1 1 iro dac 1 offset correc - tion % of v dd (%) +1.25 offset correc - tion at v dd = 5v (mv) +63 sign c1 c2 c0 value +6 1 1 1 0 +1.08 +54 +5 1 1 0 1 +0.90 +45 +4 1 1 0 0 +0.72 +36 +3 1 0 1 1 +0.54 +27 +2 1 0 1 0 +0.36 +18 +1 1 0 0 1 +0.18 +9 +0 1 0 0 0 0 0 -0 0 0 0 0 -1 0 0 0 1 -0.18 -9 -2 0 0 1 0 -0.36 -18 -3 0 0 1 1 -0.54 -27 -4 0 1 0 0 -0.72 -36 -5 0 1 0 1 -0.90 -45 -6 0 1 1 0 -1.08 -54 -7 0 1 1 1 -1.25 -63 a1 0 0 0 a2 a0 pga value 0 pga gain (v/v) 41 output- referred iro dac step size (v dd = 5v) (v) 0.369 1 0 0 1 68 0.612 2 0 1 0 95 0.855 3 0 1 1 122 1.098 4 1 0 0 149 1.341 5 1 0 1 176 1.584 6 1 1 0 203 1.827 7 1 1 1 230 2.070 table 2. pga gain settings and iro dac step size 0 0
a v dd of 5v. the output of the offset dac is fed into the output summing junction where it is gained by approximately 2.3, which increases the resulting out - put-referred offset correction resolution to 2.8mv. both the offset tc and fsotc dacs take their refer - ence from bdrive, a temperature-dependent voltage. a nominal v bdrive of 2.5v results in a step size of 0.6mv. the offset tc dac output is fed into the output sum - ming junction where it is gained by approximately 2.3, thereby increasing the offset tc correction range. the buffered fsotc dac output is available at fsotc and is connected to isrc via r ftc to correct fsotc errors. internal resistors the max1458 contains three internal resistors (r isrc , r ftc , and r temp ) optimized for common silicon prts. r isrc (in conjunction with the fso dac) programs the nominal sensor excitation current. r ftc (in conjunction with the fsotc dac) compensates the fsotc errors. both r isrc and r ftc have a nominal value of 75k . if external resistors are used, r isrc and r ftc can be dis - abled by resetting the appropriate bit (address 07h reset to zero) in the configuration register (table 3). r temp is a high-tempco resistor with a tc of +4600ppm/ c and a nominal resistance of 100k at +25 c. this resistor can be used with certain sensor types that require an external temperature sensor. internal eeprom the max1458 has a 128-bit internal eeprom arranged as eight 16-bit words. the four uppermost bits for each register are reserved. the internal eeprom is used to store the following (also shown in the memory map in table 4): max1458 1%-accurate, digitally t rimmed sensor signal conditioner _______________________________________________________________________________________ 7 figure 3. bridge excitation circuit v dd aa ? 14i isrc = i bdrive i = i isrc i src fsotc r isrc bdrive v dd r ftc external sensor fso dac fsotc dac 01h offset sign bit, soff 00h 03h offset tc sign bit, sotc pga gain, a1 description 02h eeprom address (hex) pga gain (msb), a2 05h reserved ? 04h 07h pga gain (lsb), a0 internal resistor (r ftc and r isrc ) selection 06h reserved ? 09h input-referred offset (msb) 08h 0bh input-referred offset (iro) sign bit input-referred offset (lsb) 0ah input-referred offset table 3. configuration register
max1458 configuration register (table 3) 12-bit calibration coefficients for the offset and fso dacs 12-bit compensation coefficients for the offset tc and fsotc dacs two general-purpose registers available to the user for storing process information such as serial num - ber, batch date, and check sums program the eeprom one bit at a time. the bits have addresses from 0 to 127 (7f hex). configuration register the configuration register (table 3) determines the pga gain, the polarity of the offset and offset tc coeffi - cients, and the coarse offset correction (iro dac). it also enables/disables internal resistors (r ftc and r isrc ). dac registers the offset, offset tc, fso, and fsotc registers store the coefficients used by their respective calibration/ compensation dacs. 1%-accurate, digitally t rimmed sensor signal conditioner 8 _______________________________________________________________________________________ table 4. eeprom memory map ee address contents ee address contents ee address contents ee address contents ee address contents reserved* ee address contents ee address contents 0e 0 0c 0 0f 0d 0 0a 08 0b 09 06 04 07 05 02 1 00 configuration 03 01 1e 0 1c 1 1f 1d 0 1a 18 1b 19 16 14 17 15 12 1 10 msb offset lsb 13 11 2e 0 2c 0 2f 2d 1 2a 28 2b 29 26 24 27 25 22 1 20 msb offset tc lsb 23 21 3e 0 3c 1 3f 3d 1 3a 38 3b 39 36 34 37 35 32 1 30 msb fso lsb 33 31 4e 1 4c 0 4f 4d 0 4a 48 4b 49 46 44 47 45 42 1 40 msb fsotc lsb 43 41 5e 0 5c 0 5f 5d 0 5a 58 5b 59 56 54 57 55 52 0 50 0 53 51 6e 0 6c 0 6f 6d 0 6a 68 6b 69 66 64 67 65 62 0 60 user defined bits 63 61 7e 0 7c 0 7f 7d 0 7a 78 7b 79 76 74 77 75 72 0 70 user defined bits 73 71 note: the max1458 processes the reserved bits in the eeprom. if these bits are not properly programmed, the configuration and dac registers will not be updated correctly. * the contents of the reserved ee address 50?f must all be reset to zero. = reserved bits 0 0 0 0 0 0 0 0 0 0 0
detailed description of the digital lines chip-select (cs) and write-enable (we) cs is used to enable out, control serial communica - tion, and force an update of the configuration and dac registers. a low on cs disables serial communication and places out in a high-impedance state. a transition from low to high on cs forces an update of the configuration and dac registers from the eeprom when the ??bit is zero. a transition from high to low on cs terminates pro - gramming mode. a logic high on cs enables out and serial commu - nication (see communication protocol section). we controls the refresh rate for the internal configura - tion and dac registers from the eeprom and enables the erase/write operations. if communication has been initiated (see communication protocol section), internal register refresh is disabled. a low on we disables the erase/write operations and also disables register refreshing from the eeprom. a high on we selects a refresh rate of approximately 400 times per second and enables eeprom erase/write operations. it is recommended that we be connected to v ss after the max1458 eeprom has been programmed. sclk (serial clock) sclk must be driven externally and is used to input commands to the max1458 and read eeprom con - tents. input data on dio is latched on the rising edge of sclk. noise on sclk may disrupt communication. in noisy environments, place a capacitor (0.01 f) between sclk and v ss . data input/output (dio) the dio line is an input/output pin used to issue com - mands to the max1458 (input mode) or read the eeprom contents (output mode). in input mode (the default mode), data on dio is latched on each rising edge of sclk. therefore, data on dio must be stable at the rising edge of sclk and should transition on the falling edge of sclk. dio will switch to output mode after receiving a ?ead eeprom?command, and will return the data bit addressed by the digital value in the ?ead eeprom command. after a low-to-high transition or cs, dio returns to input mode and is ready to accept more commands. communication protocol to initiate communication, the first six bits on dio after cs transitions from low to high must be 1010u0 (defined as the init sequence). the max1458 will then begin accepting 16-bit control words (figure 4). if the init sequence is not detected, all subsequent data on dio is ignored until cs again transitions from low to high and the correct init sequence is received. the ??bit of the init sequence controls the updat - ing of the dacs and configuration register from the internal eeprom. if this bit is low (u = 0), all four inter - nal dacs and the configuration register will be updated from the eeprom on the next rising edge of cs (this is also the default on power-up). if the ??bit is high, the dacs and configuration register will not be updated from the internal eeprom; they will retain their current value on any subsequent cs rising edge. the max1458 continues to accept control words until cs is brought low. max1458 1%-accurate, digitally t rimmed sensor signal conditioner _______________________________________________________________________________________ 9 figure 4. communication sequence cs sclk dio t min = 200 m s 16 clk cycles begin programming sequence control word control word control words 16 clk cycles n x 16 clk cycles x 1 0 1 d0 d0 d1 d1 cm3 cm3 0 u 0
max1458 control words after receiving the init sequence on dio, the max1458 begins latching in 16-bit control words, lsb first (figure 5). the first 12 bits (d0?11) represent the data field. the last four bits of the control word (the msbs, cm0?m3) are the command field. the max1458 supports the commands listed in table 5. erase eeprom command when an erase eeprom command is issued, all of the memory locations in the eeprom are reset to a logic ?.?the data field of the 16-bit word is ignored. important: an internal charge pump develops voltages greater than 20v for eeprom programming operations. the eeprom control logic requires 50ms to erase the eeprom. after sending a write or erase command, failure to wait 50ms before issuing another command may result in data being accidentally written to the eeprom. the maximum number of erase eeprom cycles should not exceed 100. begin eeprom write command the begin eeprom write command stores a logic high at the memory location specified by the lower seven bits of the data field (a0?6). the higher bits of the data field (a7?11) are ignored (figure 6). note that to write to the internal eeprom, we and cs must be 1%-accurate, digitally t rimmed sensor signal conditioner 10 ______________________________________________________________________________________ figure 5. control-word timing diagram sclk dio data lsb msb msb lsb lsb msb msb lsb command 16-bit configuration word d6 d9 d7 d10 d8 d11 cm0 cm2 cm2 cm3 d0 d3 d1 d4 d2 d5 figure 6. timing diagram for write eeprom operation we cs sclk dio t min = 200 m s 16 clk cycles init sequence begin eeprom write end eeprom write t wait t write n command words 16 clk cycles n x 16 clk cycles x 1 0 1 a0 d0 a0 a1 d1 a1 cm3 cm3 cm3 0 u 0 table 5. max1458 commands function erase eeprom cm2 0 cm1 0 1h hex code cm3 0 cm0 1 begin eeprom write at address 0 1 2h 0 0 read eeprom at address 0 1 3h 0 1 maxim reserved 1 0 4h 0 0 end eeprom write at address 1 0 5h 0 1 write data to configuration register 0 0 8h 1 0 write offset dac 0 0 9h 1 1 write offset tc dac 0 1 ah 1 0 write fso dac 0 1 bh 1 1 write fsotc dac 1 0 ch 1 0 no operation 0 0 0h 0 0 load register 1 1 1 1 1 1 1 0 1 1 6h, 7h, dh, eh, fh 0 0 1 1 1 0 1 1 0 1
high. in addition, the eeprom should only be written to at t a = +25 c and v dd = 5v. writing to the internal eeprom is a time-consuming process and should only be required once. all calibra - tion/compensation coefficients are determined by writ - ing directly to the dac and configuration registers. use the following procedure to write these calibration/com - pensation coefficients to the eeprom: 1) issue an erase eeprom command. 2) wait 50ms (t write ). 3) issue on end eeprom write command at address 00h. 4) wait 1ms (t wait ). 5) issue a begin eeprom write command (figure 7) at the address of the bit to be set. 6) wait 50ms. 7) issue an end eeprom write command (figure 7) using the same address as in step 5. 8) wait 1ms. 9) return to step 5 until all necessary bits have been set. 10) read eeprom to verify that the correct calibra - tion/compensation coefficients have been stored. read eeprom command the read eeprom command returns the bit stored at the memory location addressed by the lower seven bits of the data field (a0?6). the higher bits of the data field (a7?11) are ignored. note that after a read com - mand has been issued, the dio lines become an out - put and the state of the addressed eeprom location will be available on dio 200 s (t read ) after the falling edge of the 16th sclk cycle (figure 8). after issuing the read eeprom command, dio returns to input mode on the falling edge of cs. reading the entire eeprom requires the read eeprom command be issued 128 times. max1458 1%-accurate, digitally t rimmed sensor signal conditioner ______________________________________________________________________________________ 11 figure 7. begin write eeprom and end write eeprom timing diagrams sclk sclk dio data lsb msb msb lsb msb lsb command data lsb msb msb lsb command 16-bit command word ?begin eeprom write at address command lsb msb 16-bit command word ?end eeprom write at address command a0 a1 a2 a3 a4 a5 a6 0 0 0 0 0 0 0 0 1 dio a0 a1 a2 a3 a4 a5 a6 0 0 0 0 0 1 1 0 0 figure 8. read eeprom timing diagram sclk t min = 200 m s cs dio 16 clock cycles init sequence a0 x 1 0 1 0 u 0 a1 a2 a3 a4 a5 a6 0 0 0 0 0 0 0 x x ee data dio is an output pin 1 1 t read read eeprom at address command dio is an input pin
max1458 writing to the configuration and dac registers when writing to the configuration register or directly to the internal 12-bit dacs, the data field (d0?11) con - tains the data to be written to the respective register. note that all four dacs and the configuration register can be updated without toggling the cs line. every register write command must be followed by a load register command. __________ applications infor mation power-up at power up, the following occurs: 1) the dac and configuration registers are reset to zero. 2) cs transitions from low to high after power-up (an internal pull-up resistor ensures that this happens if cs is left unconnected), and the eeprom contents are read and processed. 3) the dac and configuration registers are updated either once or approximately 400 times per second (as determined by the state of we). 4) the max1458 begins accepting commands in a ser - ial format on dio immediately after receiving the init sequence. the max1458 is shipped with all memory locations in the internal eeprom uninitialized. therefore, the max1458 must be programmed for proper operation. compensation procedure the following compensation procedure was used to obtain the results shown in figure 9 and table 8. it assumes a pressure transducer with a +5v supply and an output voltage that is ratiometric to the supply volt - age. the desired offset voltage (v out at p min ) is 0.5v, and the desired fso voltage (v out(p max ) - v out(p min ) ) is 4v; thus the full-scale output voltage (v out at p max ) will be 4.5v (refer to figure 1). the procedure requires a minimum of two test pressures (e.g., zero and full scale) at two arbitrary test temperatures, t 1 and t 2 . ideally, t 1 and t 2 are the two points where we wish to perform best linear fit compensation. the following out - lines a typical compensation procedure: 1) perform coefficient initialization 2) perform fso calibration 3) perform fsotc compensation 4) perform offset tc compensation 5) perform offset calibration coefficient initialization select the resistor values and the pga gain to prevent overload of the pga and bridge current source. these values depend on sensor behavior and require some sensor characterization data, which may be available from the sensor manufacturer. if not, the data can be generated by performing a two-temperature, two-pres - sure sensor evaluation. the required sensor information is shown in table 6 and can be used to obtain the val - ues for the parameters listed in table 7. table 6. sensor information for typical prt selecting r isrc when using an external resistor, use the equation below to determine the value of r isrc , and place the resistor between isrc and v ss . since the 12-bit fso dac provides considerable dynamic range, the r isrc value need not be exact. generally any resistor value within 50% of the calculated value is acceptable. if both the internal resistors r isrc and r ftc are used, set the irs bit at eeprom address bit 7 high. otherwise, set irs low and connect external resistors as shown in figure 10. where rb(t) is the sensor input impedance at tempera - ture t1 (+25 c in this example). r rb(t k k isrc ? ? = ) 14 1 14 5 70 x x w w 1%-accurate, digitally t rimmed sensor signal conditioner 12 ______________________________________________________________________________________ 5k at +25 c typical values rb(t) 2600ppm/ c bridge impedance tcr sensor description bridge impedance tempco parameter 1.5mv/v per psi at +25 c s(t) -2100ppm/ c sensitivity tcs sensitivity tempco 12mv/v at +25 c o(t) -1000ppm/ c of fso offset otc offset tempco 0.1% fso, bslf s(p) 0 psi sensitivity linearity error as % fso, bslf (best straight-line fit) p min minimum input pressure 10 psi p max maximum input pressure
selecting r ftc when using an external resistor, use the equation below to determine the value for r ftc , and place the resistor between isrc and fsotc. since the 12-bit fsotc dac provides considerable dynamic range, the r ftc value need not be exact. generally, any resistor value within 50% of the calculated value is accept - able. this approximation works best for bulk, micromachined, silicon prts. negative values for r ftc indicate uncon - ventional sensor behavior that cannot be compensated by the max1458 without additional external circuitry. selecting the pga gain setting to select the pga gain setting, first calculate sensorfso, the sensor full-span output voltage at t1: sensorfso = s x v bdrive x d p = 1.5mv/v per psi x 2.5v x 10 psi = 0.0375v where s is the sensor sensitivity at t1, v bdrive is the sensor excitation voltage (initially 2.5v), and d p is the maximum pressure differential. then calculate the ideal gain using the following formula, and select the nearest gain setting from table 2: where outfso is the desired calibrated transducer full-span output voltage, and sensorfso is the sensor full-span output voltage at t1. in this example, a pga value of 2 (gain of +95v/v) is the best selection. determining input-referred offset (iro) the input-referred offset register is used to null any front-end sensor offset errors prior to amplification by the pga. this reduces the possibility of saturating the pga and maximizes the useful dynamic range of the pga (particularly at the higher gain values.) first, calculate the ideal iro correction voltage using the following formula, and select the nearest setting from table 1: where iroideal is the exact voltage required to perfect - ly null the sensor, o(t1) is the sensor offset voltage in v/v at +25 c, and v bdrive (t1) is the nominal sensor excitation voltage at +25 c. in this example, 30mv must be subtracted from the amplifier front end to null the sensor perfectly. from table 1, select an iro value of 3 to set the iro dac to 27mv, which is nearest the ideal value. to subtract this value, set the iro sign bit to 0. the residual output-referred offset error will be corrected later with the offset dac. determining offtc coef initial value generally, offtc coef can initially be set to 0, since the offset tc error will be compensated in a later step. however, sensors with large offset tc errors may require an initial coarse offset tc adjustment to prevent the pga from saturating during the compensation pro - cedure as temperature is increased. an initial coarse offset tc adjustment is required for sensors with an off - set tc greater than about 10% of the fso. if an initial iroideal - o t1 x v t1 - 0.012v/v x 2.5v - 30mv bdrive = ( ) ( ) [ ] = ( ) = a outfso sensorfso 4v 0.0375v 106v/v pga = = = r r x 500ppm/ c 70k x 500ppm/ c 70k ftc isrc @ @ = w tcr - tcs 2600 ppm/ c - -2100 ppm/ c | | | | w max1458 1%-accurate, digitally t rimmed sensor signal conditioner ______________________________________________________________________________________ 13 a pga programmable-gain amplifier gain r isrc iro internal (approximately 75k ) or user- supplied resistor that programs the nomi - nal sensor excitation current. input-referred offset correction dac value description iro sign parameter input-referred offset sign bit irs internal resistor selection bit off coef offset correction dac coefficient off sign offset sign bit offtc coef offset tc compensation dac coefficient offtc sign offset tc sign bit fso coef fso trim dac coefficient fsotc coef fso tc compensation dac coefficient r ftc internal (approximately 75k ) or user- supplied resistor that compensates fso tc errors. table 7. compensation components and values
max1458 coarse offset tc adjustment is required, use the follow - ing equation: where otc is the sensor offset tc error as a ppm/ c of outfso (table 6), d t is the operating temperature range in c, and offtc coef is the numerical decimal value to be loaded into the dac. for positive values, set the offtc sign bit high; for negative values, set the offtc sign bit low. if the absolute value of the offtc coef is larger than 4096, the sensor has a very large offset tc error, which the max1458 is unable to com - pletely correct. fso calibration perform fso calibration at room temperature with a full- scale sensor excitation. 1) set fsotc coef to 1000. 2) at t1, adjust fso dac until v bdrive is about 2.5v. 3) adjust offset dac (and offset sign bit, if needed) until the t1 offset voltage is 0.5v (see offset calibration section). 4) measure the full-span output (measuredv fso ). 5) calculate the ideal bridge voltage, v bideal (t1), using the following equation: note: if v bideal (t1) is outside the allowable bridge voltage swing of (v ss + 1.3v) to (v dd - 1.3v), readjust the pga gain setting. if v bideal (t1) is too low, decrease the pga gain setting by one step and return to step 2. if v bideal (t1) is too high, increase the pga gain setting by one step and return to step 2. 6) set v bideal (t1) by adjusting the fso dac. 7) readjust offset dac until the offset voltage is 0.5v (see offset calibration section). three-step fsotc compensation step 1 use the following procedure to determine fsotc coef. four variables, a?, will be used. 1) name the existing fso dac coefficient ?? 2) change fsotc dac to 3000. 3) adjust fso dac until v bdrive (t1) is equal to v bideal (t1). 4) name the existing fso dac coefficient ?? 5) readjust the offset voltage (by adjusting the offset dac), if required, to 0.5v. at this point, it is important that no other changes be made to the offset or offset tc dacs until the offset tc compensation step has been completed. step 2 to complete linear fsotc compensation, take data measurements at a second temperature, t2 (t2 > t1). perform the following steps: 1) measure the full-span output (measuredv fso (t2). 2) calculate v bideal (t2) using the following equation: 3) set v bideal (t2) by adjusting the fso dac. 4) name the current fso dac coefficient ?? 5) change fsotc dac to 1000. 6) adjust fso dac until v bdrive is equal to v bideal (t2). 7) name the fso dac coefficient ?? step 3 insert the data previously obtained from steps 1 and 2 into the following equation to compute fsotc coef: 1) load this fsotc coef value into the fsotc dac. 2) adjust the fso dac until v bdrive (t2) is equal to v bideal (t2). this completes both fso calibration and fso tc com - pensation. fsotc coef 1000 b - d 3000 c - a b - d c - a = ( ) + ( ) ( ) + ( ) v t2 v x 1 desiredv - measuredv t2 measuredv t2 bideal bdrive fso fso fso ( ) = + ( ) ( ) ? ? ? ? v t v x 1 desiredv - measuredv t measuredv t bideal bdrive fso fso fso 1 1 1 ( ) = + ( ) ( ) ? ? ? ? ? offtc coef 4096 x v t v t x 2.3 4096 x otc x fso tcs x v x 2.3 x 4096 x -1000ppm/ c x 4v -2100ppm/ c x 2.5v x 2.3 out bdrive bdrive = ( ) ( ) @ ( ) = ( ) = d d d d x t t 1357 1%-accurate, digitally t rimmed sensor signal conditioner 14 ______________________________________________________________________________________
offset tc compensation the offset voltage at t1 was previously set to 0.5v; therefore, any variation from this voltage at t2 is an offset tc error. perform the following steps: 1) measure the offset voltage at t2. 2) use the following equation to compute the correc - tion required: note: currentofftc coef is the current value stored in the offset tc dac. if the offset tc sign bit (sotc) is low, this number is negative. 3) load this value into the offset tc dac. 4) if newofftc coef is negative, set the sotc bit low; otherwise, set it high. offset tc compensation is now complete. offset calibration at this point the sensor should still be at temperature t2. the final offset adjustment can be made at t2 or t1 by adjusting the offset dac (and optionally the offset sign bit, soff) until the output (v out(p min ) ) reads 0.5v at zero input pressure. use the following procedure: 1) set offset dac to zero (offset coef = 0). 2) measure the voltage at out. 3) if v out is greater than the desired offset voltage (0.5v in this example), set soff low; otherwise set it high. 4) increase offset coef until v out equals the desired offset voltage. offset calibration is now complete. table 8 and figure 9 compare an uncompensated input to a typical compen - sated transducer output. newofftc coef currentofftc coef + 4096 v t - v t2 2.3 v t - v t2 offset offset bdrive bdrive = ( ) ( ) [ ] ( ) ( ) [ ] ? ? ? ? ? 1 1 max1458 1%-accurate, digitally t rimmed sensor signal conditioner ______________________________________________________________________________________ 15 typical uncompensated input (sensor) typical compensated transducer output offset .......................................................................... 80% fso fso .................................................................................. 15mv/v offset tc ...................................................................... -17% fso offset tc nonlinearity .................................................. 0.7% fso fso tc ......................................................................... -35% fso fso tc nonlinearity ..................................................... 0.5% fso temperature range ........................................... -40 c to +125 c v out ................................................... ratiometric to v dd at 5.0v offset at +25 c ...................................................... 0.500v 5mv fso at +25 c ......................................................... 4.000v 5mv offset accuracy over temp. range .......... 28mv ( 0.7% fso) fso accuracy over temp. range ............. 20mv ( 0.5% fso) table 8. max1458 calibration and compensation -20 -10 10 0 20 30 -50 0 50 100 150 uncompensated sensor error temperature (?) error (% fso) offset fso -0.8 -0.6 0.4 -0.2 -0.4 0 0.2 0.6 0.8 -50 0 50 100 150 compensation transducer error temperature ?c) error (% span) offset fso figure 9. comparison of an uncalibrated sensor and a temperature-compensated transducer
max1458 ratiometric output configuration ratiometric output configuration provides an output that is proportional to the power-supply voltage. when used with ratiometric a/d converters, this output provides digital pressure values independent of supply voltage. most automotive and some industrial applications require ratiometric outputs. the max1458 provides a high-performance ratiometric output with a minimum number of external components (figure 10). these external components include the fol - lowing: one power-supply bypass capacitor (c1) two optional resistors, one from fsotc to isrc, and another from isrc to v ss , depending on the sensor type one optional capacitor c2 from bdrive to v ss test system configuration the max1458 is designed to support an automated production pressure-temperature test system with inte - grated calibration and temperature compensation. figure 11 shows the implementation concept for a low- cost test system capable of testing up to 12 transducer modules connected in parallel. three-state outputs on the max1458 allow for parallel connection of transduc - ers. the test system shown in figure 11 includes a dedicated test bus consisting of five wires: two power-supply lines one analog output voltage line from the transducers to a system digital voltmeter two serial-interface lines: dio (input/output) and sclk (clock) for simultaneous testing of more than 12 sensor mod - ules, use buffers to prevent overloading the data bus. a digital multiplexer controls the chip-select signal for each transducer. 1%-accurate, digitally t rimmed sensor signal conditioner 16 ______________________________________________________________________________________ max1458 12-bit d/a - offset tc 12-bit d/a - offset configuration register 12-bit d/a - fso offset (irodac) 12-bit d/a - fsotc fsotc limit temp a = 1 v ss +5v out v dd digital interface pga cs temp we sclk dio bdrive inm isrc inp c2 0.1 m f c1 0.1 m f v ss r isrc r ftc r isrc r ftc 128-bit eeprom v dd s sensor figure 10. basic ratiometric output configuration
max1458 evaluation ____________ ________________________ development kit to expedite the development of max1458 based trans - ducers and test systems, maxim has produced the max1458 evaluation kit (ev kit). first-time users of the max1458 are strongly encouraged to use this kit. the max1458 ev kit is designed to facilitate manual pro - gramming of the max1458 and includes the following: 1) evaluation board with a silicon pressure sensor. 2) design/applications manual, which describes in detail the architecture and functionality of the max1458. this manual was developed for test engi - neers familiar with data acquisition of sensor data and provides sensor compensation algorithms and test procedures. 3) max1458 communication software, which enables programming of the max1458 from a computer (ibm compatible), one module at a time. 4) interface adapter and cable, which allow the con - nection of the evaluation board to a pc parallel port. max1458 1%-accurate, digitally t rimmed sensor signal conditioner ______________________________________________________________________________________ 17 max1458 dio out v dd cs module 1 sclk v ss v ss v dd v dd v ss test oven max1458 dio out cs module 2 sclk dio vout digital multiplexer +5v cs[1:n] cs1 bdrive inp inm bdrive inp inm bdrive inp inm cs2 csn sclk max1458 dio out cs module n sclk dvm figure 11. automated test system concept
max1458 1%-accurate, digitally t rimmed sensor signal conditioner 18 ______________________________________________________________________________________ functional diagram max1458 12-bit d/a - offset tc 12-bit d/a - offset configuration register 12-bit d/a - fso offset (irodac) 12-bit d/a - fsotc fsotc limit temp a = 1 v ss out v dd digital interface pga cs temp we sclk dio bdrive inm isrc inp v ss r isrc r ftc 128-bit eeprom v dd s chip infor mation transistor count: 7772 substrate connected to v ss
max1458 1%-accurate, digitally t rimmed sensor signal conditioner ______________________________________________________________________________________ 19 package infor mation ssop.eps
max1458 1%-accurate, digitally t rimmed sensor signal conditioner maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1998 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1998 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

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